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74AUP1G74DC-Q100,125

NXP Semiconductors

74AUP1G74DC-Q100,125 by NXP Semiconductors

NXP Semiconductors' 74AUP1G74DC-Q100,125 is a CMOS latch with 23.3ns propagation delay and 510MHz fmax. It operates b/w -40 to 125 °C, suitable for automotive applications due to AEC-Q100 screening level. The latch has a supply voltage range of 0.8V to 3.6V and comes in a small outline package with gull wing terminals.

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5

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1k+

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VNN

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Nova Conductors

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Vyrian

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One Stop Electronics

USA . 568 parts In-Stock

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Ampacity Inc.

Singapore . 417 parts In-Stock

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AZTECH Wire

Italy . 254 parts In-Stock

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Corohmni

South Africa . 288 parts In-Stock

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Microchip USA

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Semicontronic

India . 1,484 parts In-Stock

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Overview

Discover the NXP Semiconductors 74AUP1G74DC-Q100,125 latches & flip-flops, a cutting-edge solution for your automotive applications. With a compact design and advanced CMOS technology, this product offers high performance at a nominal supply voltage of 1.1V. Featuring a wide temperature range and AEC-Q100 screening level, this component ensures reliability under extreme conditions. Trust NXP Semiconductors for top-quality components that deliver superior value and efficiency to meet your automotive electronics needs.

Feature Benefit Bullets

Package Body Material: PLASTIC/EPOXY

Provides durability and protection for internal components, ensuring longevity of the latch or flip-flop.

Surface Mount: YES

Enables easy and secure mounting onto circuit boards, saving space and improving overall layout efficiency.

Screening Level: AEC-Q100

Certified for automotive applications, ensuring reliability and performance in harsh environments.

Nominal Supply Voltage / Vsup (V): 1.1

Optimal supply voltage for efficient operation and power consumption.

Propagation Delay (tpd): 23.3 ns

Low propagation delay ensures fast response times, improving overall system performance.

Maximum Operating Temperature: 125 °C

Ideal for automotive applications where high temperatures may be present, ensuring reliability and longevity.

Trigger Type: POSITIVE EDGE

Allows for precise triggering and control of the latch or flip-flop, enhancing overall system performance.

Technology: CMOS

CMOS technology offers low power consumption and high noise immunity, making it suitable for a wide range of applications.

Technical Specifications

Latches & Flip-Flops 74AUP1G74DC-Q100,125 attributes and parameters. Explore more Latches & Flip-Flops devices from NXP Semiconductors

Specs

Family:

AUP/ULP/V

JESD-30 Code:

R-PDSO-G8

Length:

2.3 mm

Logic IC Type:

No. of Bits:

1

No. of Functions:

1

No. of Terminals:

8

Maximum Operating Temperature:

125 Cel

Minimum Operating Temperature:

-40 Cel

Output Polarity:

COMPLEMENTARY

Package Body Material:

PLASTIC/EPOXY

Package Code:

Package Shape:

Package Style (Meter):

SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH

Propagation Delay (tpd):

23.3 ns

Screening Level:

AEC-Q100

Maximum Seated Height:

1 mm

Maximum Supply Voltage (Vsup):

3.6 V

Minimum Supply Voltage (Vsup):

.8 V

Nominal Supply Voltage / Vsup (V):

1.1

Surface Mount:

YES

Technology:

CMOS

Temperature Grade:

Terminal Form:

Terminal Pitch:

.5 mm

Terminal Position:

DUAL

Trigger Type:

POSITIVE EDGE

Width:

2 mm

Minimum fmax:

510 MHz

Trade Compliance

74AUP1G74DC-Q100,125 Logic ICs trade compliance attributes, and parameters.

HTS

8542.39.00.01

SB

8542.39.00.00

Manufacturer Highlights

NXP Semiconductors

NXP is a leading semiconductor company that creates cutting-edge technology to power secure connections in a smarter world. Founded in 2006, they have grown to become one of the top five global semiconductor companies and serve their customers in over 70 countries around the world.

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Management team

Executive Director, President, CEO

Kurt Sievers

Executive VP, CFO

Bill Betz

Executive VP, Chief Sales Officer

Ron Martino

Manufacturer fab locations 7

Fab name Location Fab Initiation Wafer Capacity

ICN8

Fabrication

Fab Initiation

1996

Netherlands

Nijmegen

Wafer Capacity

55,000

1996

55,000

ATMC (Austin Tech & Mfg Center)

Fabrication

Fab Initiation

1995

USA

Austin

Wafer Capacity

30,000

1995

30,000

N/A

Fabrication

Fab Initiation

1989

Germany

Boeblingen

Wafer Capacity

1989

CHD

Fabrication

Fab Initiation

1993

USA

Chandler

Wafer Capacity

30,000

1993

30,000

OHTC

Fabrication

Fab Initiation

1991

USA

Austin

Wafer Capacity

24,000

1991

24,000

New Expansion Fab

Fabrication

Fab Initiation

2026

USA

Austin

Wafer Capacity

2026

ECHO

Fabrication

Fab Initiation

2020

USA

Chandler

Wafer Capacity

10,000

2020

10,000

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