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UPD30311R-33

Renesas Electronics

UPD30311R-33 by Renesas Electronics

MATH PROCESSOR, COPROCESSOR; Terminal Form: PIN/PEG; No. of Terminals: 84; Package Code: PGA; Package Shape: SQUARE; Address Bus Width: 0;

Median Price

-

Lifecycle Status

Suppliers In-Stock

0

In-Stock Inventory

< 1k

Distributors (Availability)

Supplier In-Stock 1+ parts 100+ parts 1k+ parts 10k+ parts

Corohmni

South Africa . 23 parts In-Stock

1+ parts

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100+ parts

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1k+ parts

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10k+ parts

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23

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Technical Specifications

Math CoProcessors UPD30311R-33 attributes and parameters. Explore more Math CoProcessors devices from Renesas Electronics

Specs

Address Bus Width:

0

Boundary Scan:

NO

Maximum Clock Frequency:

33 MHz

External Data Bus Width:

0

JESD-30 Code:

S-XPGA-P84

JESD-609 Code:

e0

No. of Terminals:

84

Package Body Material:

CERAMIC

Package Code:

PGA

Package Equivalence Code:

PGA84,12X12

Package Shape:

Package Style (Meter):

GRID ARRAY

Power Supplies (V):

5

Qualification:

Not Qualified

Sub-Category:

Math Processors

Maximum Supply Voltage:

5.25 V

Minimum Supply Voltage:

4.75 V

Nominal Supply Voltage:

5 V

Surface Mount:

NO

Technology:

CMOS

Terminal Finish:

Tin/Lead (Sn/Pb)

Terminal Form:

Terminal Pitch:

2.54 mm

Terminal Position:

PERPENDICULAR

Peripheral IC Type:

Trade Compliance

UPD30311R-33 Peripheral ICs trade compliance attributes, and parameters.

HTS

8542.31.00.01

SB

8542.31.00.00

Manufacturer Highlights

Renesas Electronics

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