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EP20K400GI655-3

Altera

EP20K400GI655-3 by Altera

LOADABLE PLD; Form Of Terminal: PIN/PEG; No. of Terminals: 655; Package Code: IPGA; Package Shape: SQUARE; JESD-30 Code: S-CPGA-P655;

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Technical Specifications

Programmable Logic Devices (PLD) EP20K400GI655-3 attributes and parameters. Explore more Programmable Logic Devices (PLD) devices from Altera

IC Features

Programmable IC Type:

Organization:

4 Dedicated Inputs, 502 I/O

No. of Outputs:

496

Output Function:

Macrocell

No. of Inputs:

496

No. of Dedicated Inputs:

4

No. of Logic Cells:

16640

No. of I/O Lines:

502

Technology:

CMOS

Sub-Category:

Field Programmable Gate Arrays

Power Characteristics

Nominal Supply Voltage:

2.5

Minimum Supply Voltage:

2.375 V

Maximum Supply Voltage:

2.625 V

Power Supplies (V):

2.5,2.5/3.3 V

Temperature and Environmental Ratings

Peak Reflow Temperature:

220 °C (428 °F)

Moisture Sensitivity Level (MSL):

1

Packaging and Physical Characteristics

Package Body Material:

Ceramic, Metal-Sealed Cofired

Package Style (Meter):

Grid Array, Interstitial Pitch

Package Code:

Package Shape:

Package Equivalence Code:

SPGA655,47X47

Width:

62.484 mm

Length:

62.484 mm

Maximum Seated Height:

4.08 mm

Terminal Characteristcs

Terminal Position:

Perpendicular

Terminal Form:

No. of Terminals:

655

Terminal Pitch:

2.54 mm

Terminal Finish:

Tin Lead

Standards

JESD-30 Code:

S-CPGA-P655

JESD-609 Code:

e0

Qualified:

No

Trade Compliance

EP20K400GI655-3 Programmable ICs trade compliance attributes, and parameters.

ECCN

3A991.D

ECCN Governance

EAR

HTS

8542.39.00.01

SB

8542.39.00.00

Manufacturer Highlights

Altera

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