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LA4064V-75TN100E

Lattice Semiconductor

LA4064V-75TN100E by Lattice Semiconductor

LA4064V-75TN100E by Lattice Semiconductor is a 64 macrocell EE PLD with 8ns propagation delay, operating at up to 168MHz. Ideal for automotive applications, it features AEC-Q100 screening and in-system programmability, with 64 I/O lines and JTAG boundary scan test capability.

Median Price

$16.820

Lifecycle Status

Suppliers In-Stock

5

In-Stock Inventory

1k+

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Mouser Electronics

USA . 485 parts In-Stock

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$16.820

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$15.360

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Martec Srl

Italy . 19,355 parts In-Stock

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Vyrian

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Nova Conductors

Japan . 200 parts In-Stock

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Electronics Depot

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Corohmni

South Africa . 100 parts In-Stock

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$12.860

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Advanced Electronics

New Zealand . 40 parts In-Stock

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Ampacity Inc.

Singapore . 236 parts In-Stock

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$14.280

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Semicontronic

India . 236 parts In-Stock

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$13.923

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$13.852

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Microchip USA

USA . 1,858 parts In-Stock

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$37.100

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$36.570

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$36.310

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Continental Prestige Electronics

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A-Z Elektronik GmbH

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Argo Parts USA

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Overview

Unleash the power of innovation with the LA4064V-75TN100E by Lattice Semiconductor. As a leading manufacturer in the industry, Lattice Semiconductor delivers top-quality Programmable Logic Devices (PLD) that are versatile and reliable. With 64 macro cells and in-system programmability, this EE PLD offers endless possibilities for your projects. Whether you're working on automotive applications or high-speed designs, this device provides exceptional value, flexibility, and performance. Trust in Lattice Semiconductor to bring your ideas to life with the LA4064V-75TN100E.

Feature Benefit Bullets

Package Body Material: PLASTIC/EPOXY

This material provides good durability and resistance to environmental factors, making the PLD suitable for various applications.

Propagation Delay: 8 ns

Low propagation delay ensures quick response time of the PLD, making it efficient for time-critical operations.

Maximum Supply Voltage: 3.6 V

The high maximum supply voltage allows for flexibility in power supply options, making the PLD versatile in different voltage environments.

No. of Macro Cells: 64

With 64 macro cells, the PLD offers sufficient logic capacity to handle complex designs and tasks.

Technology Used: CMOS

CMOS technology provides low power consumption and high noise immunity, enhancing the efficiency and reliability of the PLD.

Maximum Clock Frequency: 168 MHz

The high maximum clock frequency allows for fast processing and operation speed, making the PLD suitable for high-speed applications.

Moisture Sensitivity Level (MSL): 3

With MSL level 3, the PLD is less susceptible to moisture damage during storage and handling, ensuring long-term reliability.

In-System Programmable: YES

Being in-system programmable allows for easy updates and modifications to the PLD's configuration without the need for physical reprogramming, offering flexibility and convenience.

Technical Specifications

Programmable Logic Devices (PLD) LA4064V-75TN100E attributes and parameters. Explore more Programmable Logic Devices (PLD) devices from Lattice Semiconductor

IC Features

Programmable IC Type:

In-System Programmable:

Yes

Organization:

0 Dedicated Inputs, 64 I/O

No. of Outputs:

64

Output Function:

Macrocell

No. of Inputs:

64

No. of Macro Cells:

64

No. of Dedicated Inputs:

0

No. of I/O Lines:

64

Maximum Clock Frequency:

168 MHz

Propagation Delay:

8 ns

Technology:

CMOS

Sub-Category:

Programmable Logic Devices

Power Characteristics

Nominal Supply Voltage:

3.3

Minimum Supply Voltage:

3 V

Maximum Supply Voltage:

3.6 V

Power Supplies (V):

3.3 V

Temperature and Environmental Ratings

Maximum Operating Temperature:

125 °C (257 °F)

Minimum Operating Temperature:

-40 °C (-40 °F)

Temprature Grade:

Peak Reflow Temperature:

260 °C (500 °F)

Moisture Sensitivity Level (MSL):

3

Maximum Time At Peak Reflow Temperature:

40 s

Packaging and Physical Characteristics

Package Body Material:

Plastic/Epoxy

Package Style (Meter):

Flatpack, Low Profile, Fine Pitch

Package Code:

Package Shape:

Package Equivalence Code:

TQFP100,.63SQ

Width:

14 mm

Length:

14 mm

Maximum Seated Height:

1.6 mm

Terminal Characteristcs

Terminal Position:

Quad

Terminal Form:

No. of Terminals:

100

Terminal Pitch:

.5 mm

Terminal Finish:

Matte Tin

Standards

JESD-30 Code:

S-PQFP-G100

JESD-609 Code:

e3

JTAG Boundary Scan Test:

Yes

Qualified:

No

Screening Level:

AEC-Q100

Trade Compliance

LA4064V-75TN100E Programmable ICs trade compliance attributes, and parameters.

ECCN

EAR99

ECCN Governance

EAR

HTS

8542.39.00.01

SB

8542.39.00.00

PCN

Manufacturer Highlights

Lattice Semiconductor

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.

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