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Part# Info IC Features Power Characteristics Temperature and Environmental Ratings Packaging and Physical Characteristics Terminal Characteristcs Standards
Part RoHS Manufacturer Description Programmable IC Type In-System Programmable Organization No. of Outputs Output Function No. of Inputs No. of Macro Cells No. of Product Terms No. of Dedicated Inputs No. of Logic Cells No. of I/O Lines Maximum Clock Frequency Propagation Delay Technology Architecture Sub-Category Additional Features Nominal Supply Voltage Minimum Supply Voltage Maximum Supply Voltage Power Supplies (V) Maximum Operating Temperature Minimum Operating Temperature Temprature Grade Peak Reflow Temperature Moisture Sensitivity Level (MSL) Maximum Time At Peak Reflow Temperature Package Body Material Package Style (Meter) Package Code Package Shape Package Equivalence Code Width Length Maximum Seated Height Packing Method Terminal Position Terminal Form No. of Terminals Terminal Pitch Terminal Finish JESD-30 Code JESD-609 Code JTAG Boundary Scan Test Qualified Screening Level
CY39200V388-125MGC by Cypress Semiconductor

CY39200V388-125MGC

Cypress Semiconductor

CY39200V388-125MGC by Cypress Semiconductor is a 3072 macrocell LOADABLE PLD with 10ns propagation delay. It operates at 2.5V, has 294 I/O lines, and supports JTAG boundary scan test. Ideal for applications requiring fast processing and extensive I/O capabilities in commercial temperature environments.

Loadable PLD

Yes

0 Dedicated Inputs, 294 I/O

Macrocell

3072

0

294

10 ns

CMOS

Programmable Logic Devices

Also operates at 3.3 V nominal supply

2.5

2.3 V

2.7 V

1.5/3.3,2.5/3.3 V

70 °C (158 °F)

0 °C (32 °F)

Commercial

Plastic/Epoxy

Grid Array

BGA

Square

BGA388,26X26,50

35 mm

35 mm

2.46 mm

Bottom

Ball

388

1.27 mm

Tin Lead

S-PBGA-B388

e0

Yes

No

CY39100V388B-125MGC by Cypress Semiconductor

CY39100V388B-125MGC

Cypress Semiconductor

CY39100V388B-125MGC by Cypress: 10ns Propagation Delay, 1536 Macro Cells, CMOS tech. Ideal for PLD applications with 294 I/O lines, JTAG Boundary Scan Test, and In-System Programmable feature.

Loadable PLD

Yes

0 Dedicated Inputs, 294 I/O

Macrocell

1536

0

294

10 ns

CMOS

Programmable Logic Devices

Also operates at 3.3 V nominal supply

2.5

2.3 V

2.7 V

1.5/3.3,2.5/3.3 V

70 °C (158 °F)

0 °C (32 °F)

Commercial

Plastic/Epoxy

Grid Array

BGA

Square

BGA388,26X26,50

35 mm

35 mm

2.46 mm

Bottom

Ball

388

1.27 mm

Tin Lead

S-PBGA-B388

e0

Yes

No