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SON Latches & Flip-Flops 1

Latches & Flip-Flops
Part# Info Specs
Part RoHS Manufacturer Description Additional Features Count Direction Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Maximum Frequency At Nominal Supply Maximum I (ol) Moisture Sensitivity Level (MSL) No. of Bits No. of Functions No. of Inputs No. of Ports No. of Terminals Maximum Operating Temperature Minimum Operating Temperature Output Characteristics Output Polarity Package Body Material Package Code Package Equivalence Code Package Shape Package Style (Meter) Packing Method Peak Reflow Temperature (C) Power Supplies (V) Maximum Power Supply Current (ICC) Propagation Delay (tpd) Qualification Schmitt Trigger Screening Level Maximum Seated Height Sub-Category Maximum Supply Voltage (Vsup) Minimum Supply Voltage (Vsup) Nominal Supply Voltage / Vsup (V) Surface Mount Technology Temperature Grade Terminal Finish Terminal Form Terminal Pitch Terminal Position Maximum Time At Peak Reflow Temperature (s) Total Dose (V) Trigger Type Width Minimum fmax
74LVC1G74GM,115 by NXP Semiconductors

74LVC1G74GM,115

NXP Semiconductors

74LVC1G74GM,115 by NXP Semiconductors is a CMOS latch with a fast propagation delay of 5.9 ns and operates at a nominal voltage of 3.3V. It features an automotive temperature grade, supporting -40 °C to 125 °C. Ideal for high-speed applications, it handles up to 24A current.

R-PDSO-N8

D FLIP-FLOP

175000000 Hz

24 Amp

1

1

8

125 Cel

-40 Cel

PLASTIC/EPOXY

SON

SOLCC8,.08,20

RECTANGULAR

SMALL OUTLINE

TR

260

3.3

Not Qualified

FF/Latches

3.3

YES

CMOS

AUTOMOTIVE

NO LEAD

.5 mm

DUAL

30

POSITIVE EDGE