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SSM40T02P

Silicon Standard

SSM40T02P by Silicon Standard

N-CHANNEL; Configuration: SINGLE; Surface Mount: NO; Maximum Power Dissipation (Abs): 31.25 W; No. of Elements: 1; JESD-609 Code: e0;

Median Price

-

Lifecycle Status

Suppliers In-Stock

0

In-Stock Inventory

< 1k

Technical Specifications

Power Field Effect Transistors (FET) SSM40T02P attributes and parameters. Explore more Power Field Effect Transistors (FET) devices from Silicon Standard

Specs

Configuration:

Maximum Drain Current (Abs) (ID):

28 A

Maximum Drain Current (ID):

28 A

Field Effect Transistor Technology:

METAL-OXIDE SEMICONDUCTOR

JESD-609 Code:

e0

Moisture Sensitivity Level (MSL):

1

No. of Elements:

1

Operating Mode:

ENHANCEMENT MODE

Maximum Operating Temperature:

150 Cel

Polarity or Channel Type:

Maximum Power Dissipation (Abs):

Sub-Category:

FET General Purpose Power

Surface Mount:

NO

Terminal Finish:

Tin/Lead (Sn/Pb)

Trade Compliance

SSM40T02P Transistors trade compliance attributes, and parameters.

ECCN

EAR99

ECCN Governance

EAR

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