In 2008, Taiwan Semiconductor Manufacturing Company Limited (TSMC) led the foundry segment’s entry into the mass production of an array of goods for numerous clients by utilizing its 40nm process technology. The 40nm process combined ultra-low-k connection material with 193nm immersion lithography technology to improve device performance and reduce power consumption. In addition, this method set records for the smallest SRAM (0.242µm2) and macro size in the industry.
To satisfy a wider range of client needs, TSMC expanded its 40nm process technology to provide 40nm improved LP and 40nm Ultra-low Power (ULP) processes in addition to the 40nm General Purpose (GP) and Low Power (LP) processes. The 40nm General Purpose (GP) process technology was designed for high-performance applications, such as hard disc drives, networks, gaming consoles, graphics processors, CPUs, and FPGAs. Applications including cell phones, digital television (DTV), set-top boxes (STBs), gaming, and wireless networking were the focus of the 40nm Low Power (LP) and 40nm Enhanced LP processes. Applicable to wearables and the Internet of Things is the 40nm Ultra-low Power (ULP) process.
Yield Problems
TSMC’s 40-nm yield problems surfaced earlier this year, but the company claimed that it had largely resolved the problem. However, during a conference call, graphics chip maker Nvidia Corp. discussed 40-nm capacity and yield constraints at its foundry partner–TSMC.
Reports surfaced that TSMC was having issues with its ion implanter supplier, causing a shortfall of 40-nm parts. ”Demand (at Nvidia) has far exceeded supply, particularly in the 40-nm product area; the company is in a ‘sold out’ situation, and this is likely to continue for the next several months. Virtually all products are on allocation with very lean inventories in the channel,” said Hans Mosesmann, an analyst with Raymond James & Associates, in a report.
Insights from Altera’s Stratix IV
Altera’s Introduction of 40nm FPGAs
The first 40-nm FPGAs in the world and the sole risk-free route to 40-nm ASICs in the industry were introduced by Altera with the release of the Stratix IV and HardCopy IV device families in the second quarter of 2008. With Taiwan Semiconductor Manufacturing Company (TSMC), Altera’s foundry partner, the event marked the culmination of three years of intensive planning, development, and cooperation to provide custom logic devices demonstrating uncompromising product leadership.
Advantages of the 40nm Process Node
For Altera to maintain its leadership position in providing the greatest performance, highest density, lowest power, and most affordable FPGAs and HardCopy ASICs, a solid basis is provided by the 40-nm process node. The advantages of the 40-nm process over earlier nodes, such as the 65-nm node and the more current 45-nm node, are evident. Higher integration allows semiconductor manufacturers to squeeze more functionality into a smaller physical footprint, which is one of the most alluring benefits. At the International Electron Devices Meeting (IEDM) events, where top semiconductor manufacturers showcase the outcomes of their process technology initiatives, the concrete outcomes of this type of density improvement have been reported.
Performance Advantages of 40nm Technology
There are also noticeable performance advantages with the 40-nm technology. The 40 nm minimum transistor gate lengths are approximately 38.5 percent shorter than the 65 nm gate lengths and 11 percent shorter than the 45 nm manufacturing gate lengths. Higher drive strengths at 40 nm are a result of the correspondingly lower resistance, which translates to better-performing transistors. Altera uses strained silicon processes to provide additional performance advantages. For instance, the tensile strain in NMOS transistors provided by a cap layer and the compressive strain in PMOS transistors provided by silicon germanium implanted in the source and drain are advantageous to Altera’s devices. With these strained silicon methods, electron and hole mobility can be increased by up to 30%, leading to a 40% increase in transistor performance. Altera is dedicated to providing the lowest power consumption in addition to the maximum density and performance.
Reducing Leakage Current in Altera’s Stratix IV: Techniques and Impacts
Altera employs five primary methods to reduce leakage current in its Stratix IV series, each of which impacts performance by slowing down the transistors from their maximum potential. Despite these performance impacts, Altera maintains overall device performance through calculated choices that balance performance and power consumption at the transistor level. By thoroughly analyzing circuit paths throughout the target device architecture, Altera’s IC designers can pinpoint where high-performance transistors are essential and where lower-performance transistors can be utilized to minimize leakage. This strategic approach allows the 40nm process to offer Altera’s IC designers a versatile platform for achieving both high-performance targets and aggressive power consumption goals.
Techniques for Minimizing Leakage Current and Their Consequences
1. Increasing Transistor VT (Threshold Voltage) via Doping:
- Power Reduction Impact: By simply doping, the source-to-drain leakage current is minimized.
- Performance Impact: The voltage that turns on the transistor will be higher, thus making the transistor switch faster.
2. Increasing Transistor Channel Length:
- Power Reduction Impact: Among other things, making the transistor’s channel length longer increases the resistance to the source-to-drain leakage current.
- Performance Impact: The speed of the transistor’s switching process is reduced in this particular manner.
3. Applying Thicker Gate Oxide:
- Power Reduction Impact: The gate oxide layer, which is thicker, diminishes the conductivity between the gate and the substrate.
- Performance Impact: The additional layer of oxide that is added here increases the threshold voltage of the transistor, therefore decreasing turn-on time.
4. Increasing Transistor VT via Programmable Power Technology:
- Power Reduction Impact: This secret, yet the same trick to reduce source-to-drain current also applies here.
- Performance Impact: As with the case of doping, this procedure raises the voltage that makes the transistor turn on and this accordingly reduces the speed of switching.
5. Reducing VCC (Supply Voltage)
- Power Reduction Impact: Supply voltage reduces, reducing the leakage currents in a whole device.
- Performance Impact: This reduction in supply voltage, in turn, reduces the switching speed.
Conclusion
This success of the Stratix IV series by Altera contrasted with TSMC’s problems with yield in initial production at 40nm, clearly shows that strategic planning, rigorous testing, and innovative design are everything in semiconductor manufacturing.
Using TSMC’s advanced process technology at 40nm, Altera easily outperformed its predecessors by a large margin in terms of both the performance and low power consumption of the chip. What was most important, though, was their collaboration with TSMC on resolving these problems with yield, which became instrumental in launching the Stratix IV and HardCopy IV families.
Advanced techniques employed by Altera, such as boosting transistor VT, channel lengthening, application of a thicker gate oxide, use of programmable power technology, and reduction in supply voltage, all helped keep the leakage current low while maintaining high performance. This balance helped Altera hit modern targets regarding minimum performance and maximum power consumption. This kind of experience with Altera’s 40nm process will be very conscious in guiding future challenges towards semiconductor manufacturing.
Fatima Razzaq is a freelance technical writer who served as an electrical engineering lecturer at Air University—a federally chartered public sector research university in Pakistan. Razzaq holds a Bachelor’s degree with distinction in electronic engineering from Ghulam Ishaq Khan Institute of Engineering Sciences and Technology (GIKI) and a Master’s degree in Sustainable Transportation and Electrical Power Systems from the University of Nottingham, Universidad de Oviedo, and La Sapienza University of Rome. Razzaq’s diverse work experiences in academia and industry continue to inform her prolific technical writing journey in the areas of electrical engineering, storage mechanisms, power electronics, electric vehicles, energy, and related topics.
